90 lines
3.2 KiB
Diff
90 lines
3.2 KiB
Diff
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Pending upstream inclusion
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Link: https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03573.html
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Patchwork: https://patchwork.ozlabs.org/patch/517392/
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X-Gentoo-Bug: 563162
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X-Gentoo-Bug-URL: https://bugs.gentoo.org/show_bug.cgi?id=563162
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Signed-off-by: Markos Chandras <hwoarang@gentoo.org>
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diff --git a/target-mips/cpu.c b/target-mips/cpu.c
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index 4027d0f..144eea9 100644
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--- a/target-mips/cpu.c
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+++ b/target-mips/cpu.c
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@@ -58,7 +58,9 @@ static bool mips_cpu_has_work(CPUState *cs)
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check for interrupts that can be taken. */
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_mips_hw_interrupts_pending(env)) {
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- has_work = true;
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+ if (cpu_mips_hw_interrupts_enabled(env)) {
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+ has_work = true;
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+ }
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}
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/* MIPS-MT has the ability to halt the CPU. */
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diff --git a/target-mips/cpu.h b/target-mips/cpu.h
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index c91883d..210370e 100644
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--- a/target-mips/cpu.h
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+++ b/target-mips/cpu.h
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@@ -639,23 +639,24 @@ static inline int cpu_mmu_index (CPUMIPSState *env)
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return env->hflags & MIPS_HFLAG_KSU;
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}
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-static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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+static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
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{
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- int32_t pending;
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- int32_t status;
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- int r;
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-
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- if (!(env->CP0_Status & (1 << CP0St_IE)) ||
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- (env->CP0_Status & (1 << CP0St_EXL)) ||
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- (env->CP0_Status & (1 << CP0St_ERL)) ||
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+ return (env->CP0_Status & (1 << CP0St_IE)) &&
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+ !(env->CP0_Status & (1 << CP0St_EXL)) &&
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+ !(env->CP0_Status & (1 << CP0St_ERL)) &&
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+ !(env->hflags & MIPS_HFLAG_DM) &&
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/* Note that the TCStatus IXMT field is initialized to zero,
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and only MT capable cores can set it to one. So we don't
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need to check for MT capabilities here. */
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- (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
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- (env->hflags & MIPS_HFLAG_DM)) {
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- /* Interrupts are disabled */
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- return 0;
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- }
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+ !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
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+}
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+
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+/* Check if there is pending and not masked out interrupt */
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+static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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+{
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+ int32_t pending;
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+ int32_t status;
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+ bool r;
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pending = env->CP0_Cause & CP0Ca_IP_mask;
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status = env->CP0_Status & CP0Ca_IP_mask;
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@@ -669,7 +670,7 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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/* A MIPS configured with compatibility or VInt (Vectored Interrupts)
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treats the pending lines as individual interrupt lines, the status
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lines are individual masks. */
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- r = pending & status;
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+ r = (pending & status) != 0;
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}
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return r;
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}
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diff --git a/target-mips/helper.c b/target-mips/helper.c
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index 01c4461..2d86323 100644
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--- a/target-mips/helper.c
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+++ b/target-mips/helper.c
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@@ -759,7 +759,8 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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- if (cpu_mips_hw_interrupts_pending(env)) {
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+ if (cpu_mips_hw_interrupts_enabled(env) &&
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+ cpu_mips_hw_interrupts_pending(env)) {
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/* Raise it */
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cs->exception_index = EXCP_EXT_INTERRUPT;
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env->error_code = 0;
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