79 lines
2.8 KiB
Diff
79 lines
2.8 KiB
Diff
From d54a299b83a07642c85a22bfe19b69ca4def9ec4 Mon Sep 17 00:00:00 2001
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From: Leon Alrae <leon.alrae@imgtec.com>
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Date: Wed, 9 Sep 2015 12:44:25 +0100
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Subject: [PATCH] target-mips: correct MTC0 instruction on MIPS64
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MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
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register.
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Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
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---
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target-mips/translate.c | 18 +++++++-----------
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1 files changed, 7 insertions(+), 11 deletions(-)
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diff --git a/target-mips/translate.c b/target-mips/translate.c
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index 0883782..a59b670 100644
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--- a/target-mips/translate.c
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+++ b/target-mips/translate.c
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@@ -4765,12 +4765,6 @@ static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
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tcg_temp_free_i32(t0);
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}
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-static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
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-{
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- tcg_gen_ext32s_tl(arg, arg);
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- tcg_gen_st_tl(arg, cpu_env, off);
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-}
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-
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static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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const char *rn = "invalid";
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@@ -5629,12 +5623,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case 5:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
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+ tcg_gen_st_tl(arg, cpu_env,
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+ offsetof(CPUMIPSState, CP0_VPESchedule));
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rn = "VPESchedule";
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break;
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case 6:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
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+ tcg_gen_st_tl(arg, cpu_env,
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+ offsetof(CPUMIPSState, CP0_VPEScheFBack));
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rn = "VPEScheFBack";
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break;
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case 7:
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@@ -5884,7 +5880,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case 14:
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switch (sel) {
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case 0:
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- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC));
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+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
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rn = "EPC";
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break;
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default:
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@@ -6057,7 +6053,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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switch (sel) {
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case 0:
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/* EJTAG support */
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- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC));
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+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
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rn = "DEPC";
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break;
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default:
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@@ -6160,7 +6156,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case 30:
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switch (sel) {
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case 0:
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- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
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+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
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rn = "ErrorEPC";
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break;
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default:
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--
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1.7.0.4
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